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RM0008
7.3.4
Connectivity line devices: reset and clock control (RCC)
APB2 peripheral reset register (RCC_APB2RSTR)
Address offset: 0x0C
Reset value: 0x00000 0000
Access: no wait state, word, half-word and byte access
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
USART1
SPI1
TIM1
ADC2
ADC1
IOPE
IOPD
IOPC
IOPB
IOPA
AFIO
Res.
RST
Res.
RST
RST
RST
RST
Reserved
RST
RST
RST
RST
RST
Res.
RST
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:15
Reserved, always read as 0.
Bit 14 USART1RST : USART1 reset
Set and cleared by software.
0: No effect
1: Reset USART1
Bit 13 Reserved, always read as 0.
Bit 12 SPI1RST : SPI 1 reset
Set and cleared by software.
0: No effect
1: Reset SPI 1
Bit 11 TIM1RST : TIM1 timer reset
Set and cleared by software.
0: No effect
1: Reset TIM1 timer
Bit 10 ADC2RST : ADC 2 interface reset
Set and cleared by software.
0: No effect
1: Reset ADC 2 interface
Bit 9 ADC1RST : ADC 1 interface reset
Set and cleared by software.
0: No effect
1: Reset ADC 1 interface
Bits 8:7 Reserved, always read as 0.
Bit 6 IOPERST : I/O port E reset
Set and cleared by software.
0: No effect
1: Reset I:O port E
Bit 5 IOPDRST : I/O port D reset
Set and cleared by software.
0: No effect
1: Reset I/O port D
Doc ID 13902 Rev 9
121/995
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